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octal, 16 - bit nano na aa rev. b document feedback information furnished by analog devices is believ ed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no lic ense is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781 .329.4700 ? 2014C 2015 analog devices, inc. all rights reserved. technical support www.analog.com features high p erformance high relative accuracy (inl): 3 lsb maximum at 16 bits t otal unadjusted error (tue): 0.14 % of fsr maximum offset error: 1.5 mv maximum gain error: 0.06 % of fsr maximum wide o perating r anges ?40c to +125c temperature range 2 .7 v to 5.5 v power supply easy i mplementation user selectable gain of 1 or 2 (gain pi n / gain bit ) reset to zero scale or midscale (rstsel pin) 1.8 v logic compatibility 50 mhz spi with readback or daisy chain robust 2 kv hbm and 1.5 kv ficdm esd rating 20- lead, tssop and lfcsp rohs - c ompliant p ackage s applications optical transceivers base station power amplifiers process control (plc input/output cards) industrial a utomation data acquisition systems general description the ad567 6 is a low power, octal, 16- bit buffered voltage out put digital - to - analog converter ( dac ) . the device include s a gain select pin , giving a full - scale output of v ref ( gain = 1) or 2 v ref ( gain = 2). the ad5676 dac operate s from a single 2.7 v to 5.5 v supply a nd is guaranteed monotonic by design . the ad5676 is available in 20- l ea d tssop and lfcsp packag e s . the internal power - on reset circuit and the rstsel pin of the ad5676 ensure t hat the output dac s power up to zero scale or midscale and then remain there until a valid write takes place. the ad5676 contains a per channel power - down mode that typically reduces the curre nt consumption of the device to 1 a . the ad5676 emplo y s a versatile serial peripheral interf ace ( spi ) that operates at clock rates up to 50 mhz , and contain s a v logic pin intended for 1.8 v to 5 .5 v logic. table 1 . octal nano dac + ? devices interface reference 16- bit 12- bit spi interna l ad5676r ad5672r external ad5676 not applicable i 2 c internal AD5675 r ad56 71r external AD5675 not applicable product highlights 1. high r elat ive a ccuracy (inl) 16 - bit: 3 lsb maximum . 2. ?40c to +125c temperature range . 3. 20- lead, tssop and lfcsp rohs - compliant p ackage s. functional block dia gram 12549-001 input register input register power-down logic gain x1/x2 power-on reset dac register string dac 0 string dac 7 dac register ad5676 gain gnd rstsel sdo sdi ldac sync sclk reset input register string dac 1 dac register input register string dac 2 dac register input register string dac 3 dac register input register string dac 4 dac register input register string dac 5 dac register input register string dac 6 dac register buffer v ref v out 0 buffer buffer buffer buffer buffer buffer buffer v out 1 v out 2 v out 3 v out 4 v out 5 v out 6 v out 7 v dd v logic interface logic figure 1 .
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ad5676 data sheet rev. b | page 2 of 27 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 5 timing characteristics ................................................................ 6 daisy - c hain and readback timing characteristi cs ............... 7 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 terminology .................................................................................... 17 theory of operation ...................................................................... 19 digital - to - analog converter .................................................... 19 transfer function ....................................................................... 19 dac architecture ....................................................................... 19 serial interface ............................................................................ 20 standalone operation ................................................................ 21 write and update commands .................................................. 21 daisy - chain operation ............................................................. 21 readback operation .................................................................. 22 power - down operation ............................................................ 22 load dac (hardware lda c pin) ........................................... 23 ldac mask register ................................................................. 23 hardware reset ( reset ) .......................................................... 24 reset select pin (rstsel) ........................................................ 24 amplifier gain selection on lfcsp package ......................... 24 applications informat ion .............................................................. 25 power supply recommendations ............................................. 25 microprocessor interfacing ....................................................... 25 ad5676 to adsp - bf531 interface .......................................... 25 ad5676 to sport interface ..................................................... 25 layout guidelines ....................................................................... 25 galvanically isolated interface ................................................. 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 10 /15 rev. a to rev. b added 20 - lead lfcsp ....................................................... universal change s to features section, general description section, table 1, product highlights section , and figure 1 ....................... 1 change s to tabl e 2 ............................................................................ 3 deleted figure 5; renumbered sequentially ................................. 8 chan ge to tabl e 5 ............................................................................. 8 added tabl e 6 ; renumbered sequentially .................................... 8 change to table 7 ............................................................................. 9 added figure 6 and table 8 ........................................................... 10 change to figure 10 to figure 12 ................................................. 11 change to figure 13 to figure 18 ................................................. 12 changes to figure 19, figure 20, and figure 22 ......................... 13 change to figure 25, figure 28, and figure 30 ........................... 14 change to figure 31, figure 34, figure 35 , and figure 36 ........ 15 change to figure 37 and figure 38 .............................................. 16 change s to transfer function section and output amplifiers section .............................................................................................. 19 change to tabl e 9 ........................................................................... 20 changes to write to and update dac channe l n (independent of ldac ) section ........................................................................... 21 changes to readback operation section .................................... 22 changes to ldac mask register section and table 14 ............ 23 changes to reset select pin (rstsel) section .......................... 24 added amplifie r gain selection on lfcsp section, table 16, and table 17 .................................................................................... 24 added figure 53 , outline dimensions ........................................ 27 change s to ordering guide .......................................................... 27 2/1 5 rev. 0 to rev. a changes to table 2 ............................................................................. 3 chang e to reset pulse activation time parameter, table 4 ..... 6 change to terminology section ................................................... 17 changes to transfer function section and output amplifiers section .............................................................................................. 19 changes to hardware reset ( reset ) section ............................ 24 changes to orderin g guide .......................................................... 27 10/ 14 re vision 0: initial vers i on
data sheet ad5676 rev. b | page 3 of 27 specifications v dd = 2.7 v to 5.5 v , 1.8 v v logic 5.5 v , r l = 2 k?, c l = 200 pf, a ll specifications ?40c to +12 5c , unless otherwise noted. table 2. a grade b grade test cond itions/comments parameter min typ max min typ max unit static performance 1 resolution 16 16 bits relative accuracy (inl) 2 1.8 8 1.8 3 lsb gain = 1 1.7 8 1.7 3 lsb gain = 2 differential nonlinearity (dnl) 2 0.7 1 0.7 1 lsb gain = 1 0.5 1 0.5 1 lsb gain = 2 zero code error 2 0.8 4 0.8 1.6 mv gain = 1 or gain = 2 offset error 2 ?0.75 6 ?0.75 2 mv gain = 1 ?0.1 4 ?0.1 1.5 mv gain = 2 full - scale error 2 ?0.018 0.28 ?0.018 0.14 % of fsr gain = 1 ?0.013 0.14 ?0.013 0.07 % of fsr gain = 2 gain error 2 +0.04 0.24 +0.04 0.12 % of fsr gain = 1 ?0.02 0.12 ?0.02 0.06 % of fsr gain = 2 total unadjusted error (tue) +0.03 0.3 +0.03 0.18 % of fsr gain = 1 +0.006 0.25 +0.006 0.14 % of fsr gain = 2 offset error drift 2 , 3 1 1 v/c dc power supply rejection ratio (psrr) 2 , 3 0.25 0.25 mv/v da c code = midscale, v dd = 5 v 10% dc crosstalk 2 , 3 2 2 v due to single channel, full - scale output change 3 3 v/ma due to load current change 2 2 v due to powering down (per channel) output characteristics 3 output voltage range 0 v ref 0 v ref v gain = 1 0 2 v ref 0 2 v ref v gain = 2 output current drive 15 15 ma capacitive load stability 2 2 nf r l = 10 10 nf r l = 1 k ? resistive load 4 1 1 k ? load regulation 183 183 v/ma 5 v 10%, dac code = midscale, ?30 ma i out +30 ma 177 177 v/ma 3 v 10%, dac code = midscale, ?20 ma i out +20 ma short - circuit current 5 40 40 ma load impedance at rails 6 25 25 ? power - up time 2.5 2.5 s exiting power - down mode, v dd = 5 v reference input reference input current 398 398 a v ref = v dd = v logic = 5.5 v, gain = 1 789 789 a v ref = v dd = v logic = 5.5 v, gain = 2 reference input range 1 v dd 1 v dd v gain = 1 1 v dd /2 1 v dd /2 v gain = 2 reference input impedance 14 14 k? gain = 1 7 7 k? gain = 2
ad5676 data sheet rev. b | page 4 of 27 a grade b grade test cond itions/comments parameter min typ max min typ max unit logic inputs 3 input current 1 1 a per pin input voltage low, v inl 0.3 v logic 0.3 v logic v high, v inh 0.7 v logic 0.7 v logic v pin capacitance 3 3 pf logic outputs (sdo) 3 output voltage low, v ol 0.4 0.4 v i sink = 200 a high, v oh v logic ? 0.4 v logic ? 0.4 v i source = 200 a floating state output capacitance 4 4 pf power requirements v logic 1.8 5.5 1.8 5.5 v i logic 3 3 a power - on, ?40c to +105c 3 3 a power - on, ?40c to +125c 3 3 a power - down , ?40c to +105c 3 3 a power - down, ?40c to +125c v dd 2.7 5.5 2.7 5.5 v gain = 1 v ref + 1.5 5.5 v ref + 1.5 5.5 v gain = 2 i dd normal mode 7 1.1 1.26 1.1 1.26 ma ?40c to +85c 1.1 1.3 1.1 1.3 ma ?40c to +105c all power - down modes 8 1 1.7 1 1.7 a three - state, ?40c to +85c 1 1.7 1 1.7 a power down to 1 k?, ?40c to +85c 1 2.5 1 2.5 a three - state, ?40c to +105c 1 2.5 1 2.5 a power down to 1 k?, ?40c to +105c 1 5.5 1 5.5 a three - state, ?40c to +125c 1 5.5 1 5.5 a power down to 1 k?, ?40c to +125c 1 dc specifications tested with the outputs unloaded, unless otherwise noted. upper dead band = 10 mv and exists only when v ref = v dd with gain = 1 or when v ref /2 = v dd with gain = 2. linearity calculated using a reduced code range of 256 to 65 , 280. 2 see the terminology section. 3 guaranteed by design and characterization ; not production tested. 4 channel 0, channel 1, channel 2, and channel 3 can together source/sink 40 ma. similarly , channel 4, channel 5, channel 6, and channel 7 can together source/sink 40 ma up to a junction temperature of 125 c . 5 v dd = 5 v . the ad5676 include s current limiting that is intended to protect the device during tempor ary overload conditions. junction temperature can be exc e e d ed during current limit. operation above the specified max imum operation junction temperature may impair device reliability. 6 when drawing a load current at either rail, the output voltage headroom with respect t o that rail is limited by the 2 5 ? typ ical channel res istance of the output devices. for example , when sinking 1 m a, the minimum output voltage = 25 ? 1 ma = 25 mv. 7 interface inactive. all dacs active. dac outputs unloaded. 8 all dacs powered down.
data sheet ad5676 rev. b | page 5 of 27 ac characteristics v dd = 2.7 v to 5.5 v , r l = 2 k? to gnd , c l = 200 pf to gnd , 1.8 v v logic 5.5 v , all specifications ?40c to +125c , unless otherwise noted. g uaranteed by design and characterization, not production tested. table 3. parameter min typ max unit test conditions/comments output voltage settling time 1 5 8 s ? to ? scale settling to 2 lsb slew rate 0.8 v/s digital -to - analog glitch impulse 1 1.4 nv - sec 1 lsb change around major carry , gain = 1 digital feedthrough 1 0.13 nv - sec digital crosstalk 1 0.1 nv - sec analog crosstalk 1 ?0.25 nv - sec gain = 1 ?1.3 nv - sec gain = 2 dac -to - dac crosstalk 1 ?2.0 nv - sec total ha rmonic distortion (thd) 1 , 2 ?80 db t a = 25 c , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz output noise spectral density (nsd) 1 300 nv/ hz dac code = mi dscale, b andwidth = 10 khz , gain = 2 output noise 6 v p - p 0.1 hz to 10 hz, gain = 1 signal -to - noise ratio (snr) 90 db t a = 25c, bandwidth = 20 khz, v dd = 5 v, f out = 1 khz spurious - free dynamic range (sfdr) 83 db t a = 25c, bandwidth = 20 khz, v dd = 5 v, f out = 1 khz signal -to - noise - and - distortion ratio (sinad) 80 db t a = 25c, bandwidth = 20 khz, v dd = 5 v, f out = 1 khz 1 see the terminology section. 2 digitally generated sine wave at 1 khz.
ad5676 data she et rev. b | page 6 of 27 timing characteristi cs all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltag e level of (v il + v ih )/2. see figure 2 . v dd = 2.7 v to 5.5 v , 1.8 v v logic 5.5 v , v ref = 2.5 v , a ll specifications ?40c to +125c , unless otherwise noted. table 4. 1.8 v v logic < 2 .7 v 2.7 v v logic 5.5 v parameter 1 symbol min max min max unit sclk cycle time t 1 20 20 ns sclk high time t 2 4 1.7 ns sclk low time t 3 4.5 4.3 ns sync to sclk falling edge setup time t 4 15.1 10.1 ns dat a setup time t 5 0.8 0.8 ns data hold time t 6 +0.1 ?0.8 ns sclk falling edge to sync rising edge t 7 0.95 1.25 ns minimum sync high time (single, combined, or all channel update) t 8 9.65 6.75 ns sync falling edge to sclk fall ignore t 9 4.75 9.7 ns ldac pulse width low t 10 4.85 5.45 ns sclk falling edge to ldac rising edge t 11 41.25 25 ns sclk falling edge to ldac falling edge t 12 26.35 20.3 ns reset minimum pulse width low t 13 4.8 6.2 ns reset pulse activation time t 14 132 80 ns power - up time 2 5.15 5.18 s 1 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v , 1.8 v v logic v dd . guaranteed by design and characterization; not production tested. 2 time to exit power - down to normal mode o f ad5676 operation, 32 nd clock edge to 90% of dac midscale value, with output unloaded. t 4 t 3 sclk sync sdi t 1 t 2 t 5 t 6 t 7 t 8 db23 t 9 t 10 t 11 ldac 1 ldac 2 t 12 1 asynchronous ldac update mode. 2 synchronous ldac update mode. reset t 13 t 14 v out x db0 12549-002 figure 2 . serial write operation
data sheet ad5676 rev. b | page 7 of 27 daisy -c hain and readback timing char acteristics all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 4 . v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v , v ref = 2.5 v , a ll specifications ?40c to +125c , unless otherwise noted. table 5. 1.8 v v logic < 2.7 v 2.7 v v logic 5.5 v parameter 1 symbol min max min max u nit sclk cycle time t 1 120 83.3 ns sclk high time t 2 33 25.3 ns sclk low time t 3 2.8 3.25 ns sync to sclk falling edge t 4 75 50 ns data setup time t 5 1.2 0.5 ns data hold time t 6 0.3 0.4 ns sclk falling e dge to sync rising edge t 7 16.2 13 ns minimum sync high time t 8 55.1 45 ns sdo data valid from sclk rising edge t 10 21.5 22.7 ns sclk falling edge to sync rising edge t 11 24.4 20.3 ns sync rising edge to sclk rising edge t 12 85.5 54 ns 1 maximum sclk frequency is 25 mhz or 15 mhz at v dd = 2.7 v to 5.5 v , 1.8 v v logic v dd . guaranteed by de sign and characterization; not production tested. circuit diagram and daisy - c hain and readback timing diagrams 200a i ol 200a i oh v oh (min) to output pin 20pf 12549-003 c l figure 3 . load circuit for digital output (sdo) timing specifications t 4 t 5 t 6 t 8 s d o s d i s y n c sc l k 48 24 db23 db0 db23 db0 d b 2 3 input word for dac n undefined input word for dac n + 1 input word for dac n db 0 t 11 t 12 t 10 12549-004 figu re 4 . daisy - chain timing diagram
ad5676 data she et rev. b | page 8 of 27 absolute maximum rat ings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v v logic to gnd ?0.3 v to +7 v v out x to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v logic + 0.3 v operating temperature range ?40c to +12 5c storage temperature range ?65c to +150c junction temperature 125c reflow soldering peak temperature, pb - free (j - std -020) 260c esd ratings human body model (hbm) 2 kv field - induced charged device model ( ficdm ) 1.5 kv stresses at or above those listed under absolute maximum rating s may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maxi mum operating conditions for extended periods may affect product reliability. thermal resistance the design of the thermal board requires close attention. thermal resistance is highly impacted by the printed circuit board (pcb) being used, layout, and envi ronmental conditions. table 6. thermal resistance package type ja jb jc jt jb unit 20- lead tssop (ru -20) 1 98.65 44.39 17.58 1.77 43.9 c/w 20- lead lfcsp (cp -20-8) 2 82 16.67 32.5 0.43 22 c/w 1 thermal impedance simulated values are based on a jedec 2s2p thermal test board. see jedec jesd51 2 thermal impedan ce simulated values are based on a jedec 2s2p thermal test board with nine thermal vias. see jedec jesd51. esd caution
data sheet ad5676 rev. b | page 9 of 27 pin configuration an d function descripti ons 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 1 1 v out 0 v dd v logic sdi sclk sync v out 1 v out 3 v ref reset rstse l ldac sdo v out 6 v out 7 gain v out 5 v out 4 gnd v out 2 top view (not to scale) ad5676 12549-006 figure 5 . 20 - lead tssop pin configuration table 7. 20 - lead tssop pin function descriptions pin no. mnemonic description 1 v out 1 analog output voltage from dac 1. the output amplifier has rail - to - rail operation. 2 v out 0 analog output voltage from dac 0 . the output amplifier has rail -to - rail operation. 3 v dd power supply input. the ad5676 operate s from 2.7 v to 5.5 v. decouple v dd with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 v logic digital power supply. voltage ranges from 1.8 v to 5.5 v. 5 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, data transfers in on the falling edges of the next 24 clocks. 6 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data transfers at rates of up to 50 mhz. 7 sd i serial data input. th e ad56 76 has a 24 - bit input shift register. data is clocked into the register on the falling edge of the serial clock input . 8 gain span set. when this pin is tied to gnd, all eight dac outputs have a span from 0 v to v ref . if this pin is tied to v logic , all e ight dacs output a span of 0 v to 2 v ref . 9 v out 7 analog output voltage from dac 7. the output amplifier has rail -to - rail operation. 10 v out 6 analog output voltage from dac 6. the output amplifier has rail -to - rail operation. 11 v out 5 analog output vol tage from dac 5. the output amplifier has rail -to - rail operation. 12 v out 4 analog output voltage from dac 4. the output amplifier has rail -to - rail operation. 13 gnd ground reference point for all circuitry on the d evice. 14 rstsel power - on reset. tie th is pin to gnd to power up all eight dacs to zero scale. tie this pin to v logic to power up all eight dacs to midscale. 15 ldac load dac. ldac operates in two modes, asynchronously and synchronously. pulsing this pi n low allows any or all dac registers to be updated if the input registers have new data. this allows all dac outputs to update simultaneously . this pin can also be tied permanently low. 16 sdo serial data output. use this pin to daisy - chain a number of d evices together, or use it for readback. the serial data transfers on the rising edge of sclk and is valid on the falling edge. 17 reset asynchronous reset input. the reset input is falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset is activated, the input register and the dac register are updated with zero scale or midscale, depending on the state of the rstsel pin. 18 v ref reference input voltage. 19 v out 3 analog output voltage from dac 3. the output amplifier has rail -to - rail operation. 20 v out 2 analog output voltage from dac 2. the output amplifier has rail -to - rail operation.
ad5676 data she et rev. b | page 10 of 27 12549-100 14 1 3 12 1 3 4 reset 15 v ref sdo ldac 1 1 gnd v dd sync 2 v logic sclk 5 sdi 7 v out 6 6 v out 7 8 v out 5 9 v out 4 10 nic 19 v out 1 20 v out 0 18 v out 2 17 v out 3 16 nic nic = not internal l y connected ad5676 t o p view (not to scale) figure 6 . 20 - lead lfcsp pi n configuration table 8. 20 - lead lfcsp pin function descriptions pin no. mnemonic description 1 v dd power supply input . the ad5676 operate from 2.7 v to 5.5 v. decouple v dd with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 2 v logic digital power supply. the voltage on this pin ranges from 1.8 v to 5.5 v. 3 sync active low control input. this is the frame synchronization signal fo r the input data. when sync goes low, data transfers in on the falling edges of the next 24 clocks. 4 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data transfers at rates of up to 50 mhz. 5 sdi serial data input. this device has a 24 - bit input shift register. data is clocked into the register on the falling edge of the serial clock input . 6 v out 7 analog output voltage from dac 7. the output amplifier has rail - to - ra il operation. 7 v out 6 analog output voltage from dac 6. the output amplifier has rail -to - rail operation. 8 v out 5 analog output voltage from dac 5. the output amplifier has rail -to - rail operation. 9 v out 4 analog output voltage from dac 4. the output ampl ifier has rail -to - rail operation. 10, 16 n i c no t internally connect ed 11 gnd ground reference point for all circuitry on the device. 12 ldac load dac. ldac operates in two modes, asynchronously and synchrono usly. pulsing this pin low allows any or all dac registers to be updated if th e input registers have new data. that allows all dac outputs to simultaneously update. this pin can also be tied permanently low . 13 sdo serial data output. this pin can be used to daisy - chain a number of devices together, or it can be used for readback. the serial data transfers on the rising edge of sclk and is valid on the falling edge. 14 reset asynchronous reset input. the reset input is falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset is activated, the input register and the dac register are updated with zero scale or midscale, depending on the state o f the rstsel pin. 15 v ref reference input voltage. 17 v out 3 analog output voltage from dac 3. the output amplifier has rail -to - rail operation. 18 v out 2 analog output voltage from dac 2. the output amplifier has rail - to - rail operation. 19 v out 1 analog output voltage from dac 1. the output amplifier has rail -to - rail operation. 20 v out 0 analog output voltage from dac 0. the output amplifier has rail -to - rail operation. epad exposed pad. the exposed pad must be tied to gnd.
data sheet ad5676 rev. b | page 11 of 27 typical performance charac teristi cs ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 10000 20000 30000 40000 50000 60000 70000 12549-007 inl error (lsb) code figure 7 . inl error vs. code 12549-008 dnl error (lsb) code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 10000 20000 30000 40000 50000 60000 70000 figure 8 . dnl error vs. code 12549-009 total unadjusted error (% of fsr) code ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0 10000 20000 30000 40000 50000 60000 70000 figure 9 . tue vs. code 12549-010 inl error (lsb) temperature (c) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 v dd = 5v t a = 25c v ref = 2.5v ?40 ?20 0 20 40 60 80 100 120 figure 10 . inl error vs. temperature 12549-0 1 1 dnl error (lsb) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 temperature (c) ?40 ?20 0 20 40 60 80 100 120 v dd = 5v t a = 25c v ref = 2.5v figu re 11 . dnl error vs. temperature 12549-012 total unadjusted error (% of fsr) temperature (c) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 ?40 ?20 0 20 40 60 80 100 120 v dd = 5v t a = 25c v ref = 2.5v figure 12 . tue vs. temperature
ad5676 data she et rev. b | page 12 of 27 12549-016 inl error (lsb) supply voltage (v) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 v dd = 5v t a = 25c v ref = 2.5v figure 13 . inl error vs. supply voltage 12549-017 dnl error (lsb) supply voltage (v) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 v dd = 5v t a = 25c v ref = 2.5v figure 14 . dnl error vs. supply volta ge 12549-018 total unadjusted error (% of fsr) supply voltage (v) ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 v dd = 5v t a = 25c v ref = 2.5v figure 15 . tue vs. supply voltage 12549-019 error (% of fsr) temperature (c) ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 ?40 ?20 0 20 40 60 80 100 120 v dd = 5v t a = 25c v ref = 2.5v full-scale error gain error figure 16 . gain error and full - scale error vs. temperature 12549-020 error (% of fsr) supply voltage (v) ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 full-scale error gain error v dd = 5v t a = 25c v ref = 2.5v figure 17 . gain error and f ull - scale error vs. supply voltage 12549-021 error (mv) temperature (c) ?0.6 ?0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 ?40 ?20 0 20 40 60 80 100 120 zero code error offset error v dd = 5v t a = 25c v ref = 2.5v fi gure 18 . zero code error and offset error vs. temperature
data sheet ad5676 rev. b | page 13 of 27 12549-022 error (mv) supply voltage (v) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.7 3.2 3.7 4.2 4.7 5.2 v dd = 5v t a = 25c v ref = 2.5v zero code error offset error figure 19 . zero code error and offset error vs. supply voltage 12549-023 hits i dd full scale (ma) 0 20 40 60 80 100 120 0.83 0.85 0.87 0.89 0.91 0.93 0.95 0.97 0.99 1.01 v dd = 5v t a = 25c v ref = 2.5v figure 20 . i dd histogram with external reference 12549-024 v out (v) load current (a) ?1.4 ?1.0 ?0.6 ?0.2 0.2 0.6 1.0 1.4 0 0.005 0.010 0.015 0.020 0.025 0.030 sinking ?2.7v sinking ?3v sinking ?5v sourcing ?5v sourcing ?3v sourcing ?2.7v figure 21 . headroom/footroom (?v out ) vs. load current 12549-025 v out (v) load current (a) ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v dd = 5v t a = 25c gain = 2 v ref = 2.5v 0xffff 0xc000 0x8000 0x4000 0x0000 figure 22 . source and sink capability at 5 v 12549-026 v out (v) load current (a) ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ? 0.06 ? 0.04 ? 0.02 0 0.02 0.04 0.06 v dd = 3v t a = 25c gain = 1 v ref = 2.5v 0xffff 0xc000 0x8000 0x4000 0x0000 figure 23 . source and s ink c apability at 3 v 12549-027 i dd (ma) code 1.0 1.1 1.2 1.3 1.4 1.5 1.6 0 10000 20000 30000 40000 50000 60000 70000 device 1 device 2 device 3 figure 24 . supply current (i dd ) vs. code
ad5676 data she et rev. b | page 14 of 27 12549-028 i dd (ma) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 temperature (c) ?40 ?20 0 20 40 60 80 100 120 full scale zero code external reference, full scale figure 25 . supply current (i dd ) vs. temperature 12549-029 i dd (ma) logic input voltage (v) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.7 3.2 3.7 4.2 4.7 5.2 zero code external reference, full scale full scale figure 26 . supply current (i dd ) vs. supply voltage 12549-030 i dd (ma) logic input voltage (v) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.7 3.2 3.7 4.2 4.7 5.2 zero code external reference, full scale full scale figure 27 . supply c urrent (i dd ) vs. logic input voltage 12549-031 v out (v) time (s) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 80 100 120 140 160 180 200 dac 0 dac 1 dac 2 dac 3 dac 4 dac 5 dac 6 dac 7 v dd = 5v gain = 1 t a = 25c v ref = 2.5v 1/4 to 3/4 scale figure 28 . full - scale settling time 12549-032 v dd (v) time (seconds) ?0.001 0 0.001 0.002 0.003 0.004 0.005 0.006 ?1 0 1 2 3 4 5 6 0 0.002 0.004 0.006 0.008 0.010 v out (v) v dd (v) v out 0 (v) v out 1 (v) v out 2 (v) v out 3 (v) v out 4 (v) v out 5 (v) v out 6 (v) v out 7 (v) figure 29 . power - o n reset to 0 v and mid s cale 12549-033 v out (v) time (s) 0 0.50 1.00 1.50 2.00 2.50 3.00 ?5 0 5 10 v dd = 5v t a = 25c v ref = 2.5v sync midscale, gain = 2 midscale, gain = 1 figure 30 . exiting power - down to midscale
data sheet ad5676 rev. b | page 15 of 27 12549-034 v out (v) time (s) 0.004 0.003 0.002 0.001 0 ?0.001 ?0.002 ?0.003 ?0.004 15 16 17 18 19 20 21 22 v dd = 5v gain = 1 t a = 25c v ref = 2.5v code = 0x7fff to 0x8000 energy = 1.209376nv-sec figure 31 . digital - to - analog glitch impulse 12549 - 03 5 v o u t (v) t i me ( s ) ?0 . 00 6 ?0 . 00 5 ?0 . 00 4 ?0 . 00 3 ?0 . 00 2 ?0 . 00 1 0 . 00 1 0 0 . 00 2 0 . 00 3 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 a tt ack chann e l 1 a tt ack chann e l 2 a tt ack chann e l 3 a tt ack chann e l 4 a tt ack chann e l 5 a tt ack chann e l 6 a tt ack chann e l 7 figure 32 . analog crosstalk 12549-036 v out (v) time (s) ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 0.012 0 2 4 6 8 10 12 14 16 18 20 a tt ack chann e l 1 a tt ack chann e l 2 a tt ack chann e l 3 a tt ack chann e l 4 a tt ack chann e l 5 a tt ack chann e l 6 a tt ack chann e l 7 figure 33 . dac - to - dac crosstalk 1 12549-038 ch1 5v m1.0sec a ch1 401mv figure 34 . 0.1 hz to 10 hz output no ise 12549-040 nsd (nv/hz) frequency (hz) 0 200 400 600 800 1000 1200 10 100 1k 10k 100k 1m full scale midscale zero scale v dd = 5v t a = 25c gain = 1 v ref = 2.5v figure 35 . noise spectral density (nsd) 12549-037 dbv frequency (khz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2 4 6 8 10 12 14 16 18 20 v dd = 5v t a = 25c v ref = 2.5v figure 36 . t hd at 1 khz
ad5676 data she et rev. b | page 16 of 27 12549-039 time (ms) v out (v) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 0nf 0.1nf 1nf 4.7nf 10nf v dd = 5v gain = 1 t a = 25c v ref = 2.5v figure 37 . settling time vs. capacitive load 12549-041 v out (v) time (s) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 80 100 120 140 160 180 200 dac 0 dac 1 dac 2 dac 3 dac 4 dac 5 dac 6 dac 7 v dd = 5.5v gain = 1 t a = 25c v ref = 2.5v 1/4 to 3/4 scale figure 38 . settling ti me, 5.5 v 12549-042 v out at midscale (v) v out at zero scale (v) time (s) 0 0.1 0.2 0.3 0 1 2 3 ?20 0 20 40 60 reset midscale, gain = 1 zero scale, gain = 1 figure 39 . hardware reset 12549 - 043 band w i d t h (d b ) f r eq u enc y (h z) ?3 0 ?2 0 ?1 0 0 1 k 10 k 100 k 1 m 10 m v dd = 5v t a = 25c externa l reference = 2.5 v , 0.1v p-p gain = 1 v out = ful l scale figure 40 . multiplying bandwidth, external reference
data sheet ad5676 rev. b | page 17 of 27 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integr al nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. differential nonlinearity (dnl) d nl is the difference between the measured change and the ideal 1 lsb chan ge between any two adjacent codes . a specified dnl of 1 lsb maximum ensures monotonicity. th e ad5676 is guaranteed monotonic by design. zero code error zero code error is a measurement of the o utput error when zero code (0x0000) is loaded to the dac register. ideally, the output is 0 v. the zero code error is always positive because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output ampl ifier. zero code error is expressed in mv. full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full - scale error is expressed in perc ent of full - scale range (% of fsr) . gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed as % of fsr. offset error drift offset error drift is a measurem ent of the change in offset error with a change in temperature. it is expressed in v/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured with code 256 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v o ut to th e change in v dd for full - scale output of the dac. it is measured in mv/v . v ref is held at 2 v, and v dd is varied by 10%. output voltage settling time output voltage settling time is the amount of time it takes for the out put of a dac to settle to a specified level for a ? to ? full - scale i nput ch ange and is measured from the rising edge of sync . digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input co de in the dac register changes state. it is normally specified as the area of the glitch in nv - s ec , and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) . digital feedthrough digital feedthrou gh is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv - s ec , and measured with a full - scale code change on the data bus, that is, fro m all 0s to all 1s and vice versa. noise spectral density (nsd) nsd is a measurement of the internally generated random noise. random noise is characterized as a spectral density (nv/hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. dc crosstalk dc crosstalk i s the dc change in the output level of one dac in respo nse to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed i n v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change ( all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv - s ec . analog crosstalk analog crosstalk is the glitch impu lse transferred to the output of one dac due to a change in the output of another dac. to measure analog crosstalk, load one of the input registers with a full - scale code change (all 0s to all 1s and vice versa). then , execute a software lda c and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv - s ec . dac -to - dac crosstalk dac - to - dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa) , using the write to and update command s while monitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv - s ec .
ad5676 data she et rev. b | page 18 of 27 multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this . a sine wave on the reference with full - scale code loaded to the da c appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) t hd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. thd is measured in d ecibels .
data sheet ad5676 rev. b | page 19 of 27 theory of operation digital - to- analog converter t he ad5676 is an octal 16 - bit, serial input, voltage output dac . the device operate s from supply voltages of 2.7 v to 5.5 v. data is written to the ad5676 in a 2 4 - bit word format via a 3 - wi re serial interface. th e ad5676 incorporate s a power - on reset circuit to ensure that the dac output powers up to a kno wn output state. the device also has a software power - down mode that reduces the typical current consumption to typically 1 a . transfer function the gain of the output amplifier can be set to 1 or 2 using the gain select pin (gain) on the tssop package or the gain bit on th e lfcsp package. when the gain pin is tied to gnd, all e ight dac outputs have a span from 0 v to v ref . when the gain pin is tied to v logic , all eight dacs output a span of 0 v to 2 v ref . when using the lfcsp package , the gain bit in the gain setup register is used to set the gain of the output amplifier. the gain bit is 0 by default. when the gain bit is 0 the output span of all eight dacs is 0 v to v ref . when the gain bit is 1 the output span of all eight dacs is 0 v to 2 v ref . the gain bit is ignored on the tssop package. dac architecture the dac architect ure implements a segmented string dac with an internal output buffer. figure 41 shows the internal block diagram. input register dac register resistor string ref (+) v ref gnd ref (?) v out x gain (gain = 1 or 2) 12549-044 figure 41 . single dac channel architecture block diagram figure 42 shows t he simplified segmented r esistor string dac structure . the code loaded to the dac register determines the switch on the string that is connected to the output buffer. because each resistance in the string has the same value, r, the string dac is guaranteed monotonic. r r r r r to output amplifier v ref 12549-045 figure 42 . simplified resistor string structure output amplifiers the output buffer amplifier generate s rail - to - rail voltages on its output, which gives an output range of 0 v to v dd . the actual range depends on th e value of v ref , the gain setting , the offset error , and the gain error. the output amplifiers can driv e a load of 1 k? in parallel with 10 n f to gnd. the slew rate is 0.8 v/s with a typical ? to ? scale settling time of 5 s.
ad5676 data she et rev. b | page 20 of 27 serial interface t he ad5676 has a 3 - wire serial interfa ce ( sync , sclk, and s di ) that is compatible with spi, qspi ? , and microwire interface stan dards as well as most dsps. see figure 2 for a timing diagram of a typi cal write sequence. the ad5676 c ontain s an sdo pin that allow s the user to daisy chain multiple devices together (see the daisy - chain operation section) or for readback . input shift registe r the input shift register of the ad5676 is 2 4 bits wide. data is loaded msb first (db2 3 ) , and t he first four bits are the command bits, c3 to c0 (see ta ble 9 ), followed by the 4 - bit dac address bits, a 3 to a0 (see table 10) , and finally , the 16- bit data - word. the data - word comprises 16- bit input code, followed by zero, two , or four dont care bits . these data bit s are transfe rr ed to the input register on the 24 falling edges of sclk and are updated on the rising edge of sync . comm ands execute on individual dac channels, combined dac channels , or on all dacs , depending on the address bits selecte d . table 9 . command bit definitions command c3 c2 c1 c0 description 0 0 0 0 no operation 0 0 0 1 write to input register n (where n = 1 to 8, depending on the dac selected from the address bits in table 10 ), dependent on ldac 0 0 1 0 update the dac register with contents of input register n 0 0 1 1 write to and update dac channel n 0 1 0 0 power down/power up the dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software reset (power - on reset) 0 1 1 1 gain setup register (lfcsp package only) 1 0 0 0 set up the dcen register (daisy - chain enable) 1 0 0 1 set up the readback register (readback enable) 1 0 1 0 update all channels of the input register simultaneously with the input data 1 0 1 1 update all channels of the dac register and input register simultaneously with the input data 1 1 0 0 reserved 1 1 1 1 reserved table 10 . address bits and s elected dacs address bits selected output dac channel 1 a3 a2 a1 a0 0 0 0 0 dac 0 0 0 0 1 dac 1 0 0 1 0 dac 2 0 0 1 1 dac 3 0 1 0 0 dac 4 0 1 0 1 dac 5 0 1 1 0 dac 6 0 1 1 1 dac 7 1 any combination of dac channels can be selected using the addre ss bits. address bits command bits a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 c2 c1 c0 db23 (msb) db0 (lsb) data bits 12549-046 figure 43 . i nput shift register content
data sheet ad5676 rev. b | page 21 of 27 standalone operation the write sequence begins by bringing the sync line low. data from the s di line is clocked into the 24 - bit input shift regis ter on the falling edge of sclk . after the last of the 24 data bit s is clocked in , bring sync high . the programmed function is then executed, that is, an ldac dependent change in the dac register contents and/or a change in th e mode of operation occurs . if sync is taken high at a clock before the 24 th clock, it is considered a valid frame , and invalid data may be loaded to the dac. bring sync high for a minimum of 9.65 ns (single channe l, see t 8 in table 4 ) before the next write sequence so that a falling edge of sync can initiate the next write sequence. idle sync at the rails between write sequences for even lower power operation. t he sync line is kept low for 2 4 falling edges of sclk, and the dac is updated on the rising edge of sync . when data is transferred into the input register of the addressed dac, all dac registers and outputs update by taking ldac low while the sync line is high. write and update com mands write to input register n (dependent on ldac ) command 0001 allows the user to write to the dedicated input re gister for each dac individually. when ldac is low , the input register is transparent (if not controlled by the ldac mask register). update dac register with contents of input register n command 0010 loads the dac regist ers and outputs with the contents of the selected input registers and update s the dac outputs directly. write to and update dac channel n (independent of ldac ) command 0011 allows the user to write to the dac registers and updates the dac outputs directly. bit d7 to bit d0 determine which dacs have data from the input register transferred to the dac register. setting a bit to 1 transfers data from the input register to the appropriate dac register. daisy - chain operation for systems that c ontain several dacs , the sdo pin can daisy chain several devices toge ther and is enabled through a software executable daisy - chain ena bl e (dcen) command. command 1000 is reserved for this dcen function (see table 9 ). the daisy - chain mod e is enabled by setting bit db 0 in the dcen register. the default setting is standalone mode, where db0 = 0 . tabl e 11 shows how the state of the bit corresponds to the mode of operation of the device. table 11 . daisy - chain enable (dcen ) register db0 description 0 standalone mode (default) 1 dcen mode 68hc11* miso sdi sclk mosi sck pc7 pc6 sdo sclk sdo sclk sdo sdi sdi sync sync sync ldac ldac ldac ad5676 ad5676 ad5676 *additional pins omitted for clarity. 12549-047 figure 44 . daisy - chaining the ad5676 the sclk pin is continuously applied to the input shift register when sync is low. if more than 2 4 clock pulses are applied, the data ripples out of the input shift register and appears on the sdo line. this data is clock ed out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the s di input on the next dac in the chain, a daisy - chain interface is constructed. ea ch dac in the system requires 24 clock pulses. t herefore, the total numb er of clock cycles must equal 24 n, where n is the total number of devices updated. if sync is taken high at a clock that is not a multiple of 24 , it is considered a valid frame , and invalid data may be loaded to the dac . when the ser ial transfer to all devices is complete, sync goes high , which latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register . the serial clock can be continuou s or a gated clock. i f sync is held low for the correct number of clock cycles, a continuous sclk source is used. in gated clock mode, use a burst clock containing the exact number of clock cycles, and take sync high after the final clock to latch the data.
ad5676 data she et rev. b | page 22 of 27 readback operation readback mode is invoked through a software executable readback command. i f the sdo output is disabled via the d aisy - chain mode disable bit in the control register, it is enabled automat ically for the duration of the read operation, after which it is disabled again. command 1 00 1 is reserved for the readback function. this command, in association with the address bits , a3 to a0 , select s the dac input register to read . note that , during rea dback, only one da c register can be selected . the remaining data bits in the writ e sequence are dont care bits. during the next spi write, the data appearing on the sdo output contains the data from the previously addressed register. for example, to read back the dac register for channel 0 , implement the following sequence: 1. write 0x90 0000 to the ad5676 input register. this configures the device for read mode with the dac register of channel 0 sel ected. note that all data bits , db15 to db0 , are dont care bits. 2. follow this with a se cond write, a no operation ( nop ) condition, 0x0 00000. during this write, the data from the register is clocked out on the sdo line. db23 to db20 contain undefined data , and the last 16 bits contain the db19 to db4 dac register contents. when sync is high the sdo pin is driven by a weak latch which holds the last data bit. the sdo pin can be overdriven by the sdo pin of another device , thus allowing multi ple devices to be read using the same spi interface. power - down operation the ad5676 provides two separate power - down mode s. command 0100 is designa ted for the power - down function (see table 9 ). these power - down modes are software programmable by setting 16 bits, bit db 15 to bit db0 , in the input shift register. there are two bits associated with each dac chan nel. table 12 shows how the state of the two bits corresponds to the mode of operation of the device. table 12 . modes of operation operating mode pd 1 pd 0 normal operation 0 0 power - dow n modes 1 k ? to gnd 0 1 t hree - state 1 1 any or all dacs (dac 0 to dac 7 ) power down to the selected mode by setting th e corresponding bits . see tabl e 13 for the contents of the input shift register durin g the power - down/ power - up operation. when both bit pd 1 and bit pd0 in the input shift register are set to 0, the device work s normally with its normal powe r consumption of 1.1 ma typically . however, for th e two power - down modes, the supply current falls t o 1 a typically . not only does the s upply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values . this has the advantage that the output impedance of the devices are known whil e the devices are in power - down mode. there are two different power - down options. the output is connected internally to gnd t hrough either a 1 k? resistor , or it is left open - circuited ( three - state). the output stage is shown in figure 45. resistor network v out x dac power-down circuitry amplifier 12549-048 figure 45 . output stage during power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry shut down when power - down mode is activated. however, the contents of the dac register are unaffected when in power - down. the dac register update s while the device is in power - down mode. the time required to exit power - down is typically 5 s for v dd = 5 v . table 13 . 24 - bit input shift register co ntents of power - down/power - up operation 1 [ db23:db20 ] db19 [ db18:db16 ] dac 7 dac 6 dac 5 dac 4 dac 3 dac 2 dac 1 dac 0 [ db15: b14 ] [ db13: b12 ] [ db11: b10 ] [ db9:db8 ] [ db7:db6 ] [ db5:db4 ] [ db3:db2 ] [ db1:db0 ] 0100 0 xxx [ pd1:pd0 ] [ pd1:pd0 ] [ pd1:pd0 ] [ pd1:p d0 ] [ pd1:pd0 ] [ p d 1:pd0 ] [ pd1:pd0 ] [ pd1:pd0 ] 1 x means dont care.
data sheet ad5676 rev. b | page 23 of 27 load dac ( hardware ldac p in ) the ad5676 dac has a double buffered interface consisting of two banks of registers: inp u t registers and dac registers. the user can write to any combination of the input registers. updates to the dac register are controlled by the ldac pin. sync sclk v out x dac register interface logic output amplifier ldac sdo sdi v ref input register 16-bit dac 12549-049 figure 46 . simplified diagram of input loading circuitry for a single dac instantaneous dac updating ( ldac held low ) ldac is held low while data is clocked into the inpu t register using command 0001 . both t he addressed input register and the dac register are updated on the rising edge of sync and the output begins to change (see table 15) . deferred dac updating ( ldac is pulsed low ) ldac is held high while da ta is clocked into the input register using command 0001 . all dac outputs are asynchronously updated by taking ldac low after sync is taken high. the update occurs on the falling edge of lda c . ldac mask register command 0101 is reserved for this hardware ldac function. address bits are ignored. writi ng to the dac using command 0101 loads the 8 - bit ldac register (db 7 to db0). the defaul t for each channel is 0; that is, the ldac pin works normally. setting the bits to 1 forces this dac channel to ignore transitions on the ldac pin, regardless of the state of the hardware ldac pin . this flexibility is use ful in applications where the user wants to select which channels respond to the ldac pin . table 14. ldac overwrite definition load ldac register ldac bits (db 7 to db0) ldac pin ldac operation 00000000 1 or 0 determined by the ldac pin. 11111111 x 1 dac channels update and override the ldac pin. dac channels see ldac as 1 . 1 x mean s dont care. the ldac register gives the user extra flexibility and control over the hardware ldac pin (see table 14 ). setting the ldac bits (db0 to db 7 ) to 0 for a dac channel means that th e update f or this channe l is controlled by the hardware ldac pin. table 15. write commands and ldac pin truth table 1 command des cription hardware ldac pin state input register contents dac register contents 0001 write to input register n ( d ependent on ldac ) v logic data u pdate no change (no update) gnd 2 data u pdate data u pdate 0010 update th e dac r egister with contents of input register n v logic no c hange updated with i nput register contents gnd no c hange updated with i nput register contents 0011 write to and update dac channel n v logic data u pdate data u pdate gnd data u pdate data u pd ate 1 a high to low hardware ldac pin transition always updates the contents of the dac register with the contents of the input register on channels that are n ot masked (blocked) by the ldac mask register. 2 when ldac is permanently tied low, the ldac mask bits are ignored.
ad5676 data sheet rev. b | page 24 of 27 hardware reset ( reset ) the reset pin is an active low reset that allows the outputs to be cleared to either zero scale or midscale . the clear code value is user selectable via the reset sel ect p in . it is necessary to keep the reset pin low for a minimum time (see table 4 ) to complete the operation (see figure 2 ). when the reset signal is returned high, the output remains at the cleared value until a new value is programmed. while the reset pin is low, t he outputs cannot be updated with a new value. a software executable reset function is also available that rese ts the dac to the p ower - on reset code. command 0110 is designated for this software reset function (see table 9 ). any events on the ldac or reset pins during power - on reset are i gnored . reset select p in (rstsel) the ad5676 contain s a power - on reset circuit that controls the output voltage durin g power - up. by connecting the r stsel pin low, the output powers up to zero sca le. note that this is outside the linear region of the dac; by connecting the rstsel pin high, v out x power up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. the rstsel pin is only available on the tssop package. when the ad5676 lfcsp package is used the outputs power up to 0 v . amplifier gain selec tion on lfcsp packag e the output amplifier gain setting for the lfcsp package is determined by the state of bit db2 in the gain setup register (see table 16 and table 17). table 16 . gain setup register bit description db2 amplifier gain setting db2 = 0 ; amplifier gain = 1 (default) db2 = 1 ; amplifier gain = 2 table 17 . 24 - bit input s hift register contents for gain setup command db23 (msb) db22 db21 db20 db19 to db3 db2 db1 db0 (lsb) 0 1 1 1 dont care gain reserved; set to 0 reserved; set to 0
data sheet ad5676 rev. b | page 25 of 27 applications information power supply recommendations the ad5676 is typically powered by the following supplies: v dd = 3.3 v and v logic = 1.8 v. the adp7118 can be used to power the v dd pin. the adp160 can be used to power the v logic pin. this setup is shown in figure 47. the adp7118 can operate from input voltages up to 20 v. the adp160 can operate from input voltages up to 5.5 v. 12549-057 1.8v: v logic 3.3v: v dd 5v input adp160 ldo adp7118 ldo figure 47. low noise power solution for the ad5676 microprocessor interfacing microprocessor interfacing to the ad5676 is via a serial bus that uses a standard protocol that is compatible with dsp processors and microcontrollers. the communications channel requires a 3-wire or 4-wire interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5676 requires a 24-bit data-word with data valid on the rising edge of sync . ad5676 to adsp-bf531 interface the spi interface of the ad5676 can easily connect to industry- standard dsps and microcontrollers. figure 48 shows the ad5676 connected to the analog devices, inc. blackfin? dsp. the blackfin has an integrated spi port that can connect directly to the spi pins of the ad5676. adsp-bf531 sync spiselx sclk sck sdi mosi ldac pf9 reset pf8 ad5676 12549-053 figure 48. adsp-bf531 interface ad5676 to sport interface the analog devices adsp-bf527 has one sport serial port. figure 49 shows how a sport interface controls the ad5676. adsp-bf527 sync sport_tfs sclk sport_tsck sdi sport_dto ldac gpio0 reset gpio1 ad5676 12549-054 figure 49. sport interface layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. design the printed circuit board (pcb) on which the ad5676 is mounted so that the ad5676 lies on the analog plane. the ad5676 must have ample supply bypassing of 10 f in parallel with 0.1 f on each supply, located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor must have low effective series resistance (esr) and low effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. in systems where many devices are on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. the gnd plane on the device can be increased (as shown in figure 50) to provide a natural heat sinking effect. ad5676 gnd plane board 12549-055 figure 50. pad connection to board
ad5676 data sheet rev. b | page 26 of 27 galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that may occur. i coupler? products from analog devices provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5676 makes the device ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 51 shows a 4 - channel isolated interface to the ad5676 using an adum1400 . for further information, visit www.analog.com/icoupler . encode serial clock in controller adum1400 1 serial data out sync out load dac out decode to sclk to sdi to sync to ldac v ia v oa encode decode v ib v ob encode decode v ic v oc encode decode v id v od 1 additional pins omitted for clarity. 12549-056 figure 51 . isolated interface
data sheet ad5676 rev. b | page 27 of 27 outline dimensions compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarity 0.10 figure 52 . 20 - lead thin shrink sma ll outline package [tssop] (ru - 20) dimensions shown in mi llimeters 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 020509-b bot t om view top view exposed pa d pin 1 indic a t or 4.10 4.00 sq 3.90 se a ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 2.75 2.60 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 53 . 20 - lead lead frame chip scale package [lfcsp] 4 mm 4 mm body and 0.75 mm package height (cp - 20 - 8) dimensions shown in millimeters ordering guide model 1 resolution temperature range accuracy package descript ion package option ad5676aruz 16 bits ?40c to +125c 8 lsb inl 20- lead thin shrink small outline package [tssop] ru - 20 ad5676aruz - reel7 16 bits ?40c to +125c 8 lsb inl 20- lead thin shrink small outline package [tssop] ru - 20 ad5676bruz 16 bits ?40c to +125c 3 lsb inl 20- lead thin shrink small outline package [tssop] ru - 20 ad5676bruz - reel7 16 bits ?40c to +125c 3 lsb inl 20- lead thin shrink small outline package [tssop] ru - 20 ad5676acpz - reel7 16 bits ?40c to +125c 8 lsb inl 20- lead lead fra me chip scale package [lfcsp] cp - 20- 8 ad5676acpz - rl 16 bits ?40c to +125c 8 lsb inl 20- lead lead frame chip scale package [ lfcsp ] cp - 20- 8 ad5676bcpz - reel7 16 bits ?40c to +125c 3 lsb inl 20- lead lead frame chip scale package [lfcsp] cp - 20- 8 ad5676 bcpz - rl 16 bits ?40c to +125c 8 lsb inl 20- lead lead frame chip scale package [ lfcsp ] cp - 20- 8 eval - ad5676sdz evaluation board 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2014 C 2015 analog devices, in c. all rights reserved. trademarks and registered trade marks are the property of their respective owners. d12549 - 0- 10/15(b)

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